Ofertes d'ocupació per a Màrqueting i Negoci a Gipuzkoa

• Nivell d'experiència---
• Tipus de contracteTemporal
• Publicada11 de gen.

IoT Spring

Tecnun - Escuela de Ingeniería-Universidad de Navarra

Tecnun-School of Engineering, belongs to the University of Navarra. The aim of the School is to contribute to the professional training, scientific and human development of future engineers. Since its creation in the spring of 1961, it has maintained a balance between teaching, research and service to society, making these activities complement each other.

It currently has two sites campus: the older site, located at the university campus in the Ibaeta district, is made up of the laboratory buildings, the teaching and representation building completed in 1989, and a multipurpose building erected in 1996. The other site is located in the Miramon Technology Park and includes classrooms and research laboratories in the areas of Electricity, Electronics and Communications.

Job Description

The PhD student will work on a project framed in the use of integrable power systems for low-power applications. In particular, the PhD student will work on the modelling with VERILOG-A of different sources of energy generation (triboelectric, piezoelectric, photovoltaic, RF) to include them in the design of integrated circuits for energy management. The doctoral student will also characterize integrated circuits both by simulation and once manufactured.

The group to which the PhD student will join (COMMUNICATION

INTEGRATED CIRCUITS) has more than 20 years of experience in the

design of integrated circuits, especially for low power and very high

frequency applications. The group composed by 6 doctors and 3 PhD

students.

Tecnun, the Engineering School of the University of Navarra offers a 3-

year doctoral contract at its Technological Campus in San Sebastian

(Spain).

Thesis should be completed in 3 years.

Working Schedule

• 7.75 hours per day.
• Flexible timetable: start between 8:00 and 9:30.
• Summer timetable: Only mornings starting June 15th and finishing August 31st (5.5 hours).
  
  

• 23 working days + Christmas holidays (24-Dec to 2-Jan).
  
  

• CADENCE
• VERILOG
• LABVIEW.
  
  

• Experience in design and Characterization of Integrated circuits will be
  
  

• Cover letter describing your motivation as a thesis candidate.
• Updated CV
• Undergraduate and Master´s degree transcripts.